1. Field of the Invention
The present invention relates to smoothing technique without using special means for smoothing in a forming method of a semiconductor device which has a multilayered structure including different layers.
In the present specification, the semiconductor device has a multilayered structure including different layers contains a transistor, particularly a field-effect type of transistor, typically a MOS (Metal Oxide Semiconductor) transistor and a thin film transistor (TFT), a device using capacitance, an apparatus containing a circuit provided with the above-described devices, and an electric appliance containing the apparatus in a system.
2. Description of the Related Art
In recent years, a demand for down sizing, lightweight, low-cost is increasing more and more in an electric appliance containing a semiconductor device such as a video camera, a digital camera, a projector, a personal computer, a mobile computer, a mobile phone, and an electronic book. It is natural for users to demand for better performance even if the electric appliance is downsized and lightened, and the better performance is being demanded in the electric appliance. A function and the performance of the electric appliance depend on characteristics of LSI which constitutes a system of the electric appliance and characteristics of a display apparatus in a display portion of the electric appliance. Accordingly, research and development on miniaturization and integration concerning the semiconductor device such as the LSI and concerning a bright display and a microdisplay is being actively done. By improving a degree of the miniaturization and the integration, the more functions can be mounted on one chip, which permits the above-described demand for the down sizing, the lightweight and the low-cost of the electric appliance to be satisfied, and in the display apparatus finer image display can be realized by increasing the number of pixels.
And a technical development on the integration is proceeding in order to realize a system-on-chip in which devices such as an MPU, a memory, and an I/O interface constituting a system are mounted on one chip in monolithic and high speed, high reliability, and low electrical power consumption satisfy or a system-on-panel in which the system (functional circuit) is formed (mounted) on the same substrate as the panel.
It is not too much to say that a processing technique and an etching technique by reduced projection exposure decides a level of the miniaturization for proceeding integration and miniaturization of the semiconductor device. It is necessary to consider a surface of a substrate processed by projection exposure, though there is an issue of performance of a reduced projection aligner itself.
For example, in the semiconductor device formed by a multilayer including a plurality of layers with various materials and formed patterns, in case that the smoothing treatment is not done, as shown in FIG. 1A, when a second layer 2 is formed on a first layer 1 and a third layer 3 is formed on the second layer 2, a structure having a step reflecting difference of elevation between the first layer 1 and the second layer 2 is formed. In the same way, as a fourth layer 4 is formed on the third layer 3 and a fifth layer 5 is formed on the fourth layer 4, a resultant step 6 is increased.
Particularly, though wirings including a conductive film tend to reduce a line width for increasing integration, since the reduction of the line width increases resistance of the wirings, the increment of the resistance of the wirings is controlled by increasing a film thickness of the wirings. Consequently, the step (the evaluation between a convex portion and a concave portion in the semiconductor device) is increasing.
When the semiconductor device having an uneven shape on its surface is applied with a miniaturization treatment, processing according to a design can not be done because a focus of projection is warped by the uneven surface of the semiconductor device. When a film having the uneven surface is deposited, there is a problem that disconnection is created, because some materials for deposition have poor coverage. Since a focus margin is reduced in case of exposure treatment as a dimension to be processed is miniaturized, it is thought that there is necessity making a surface where the step of concavity and convexity exists within the focus margin.
In order to smooth the surface of the semiconductor device, a technique that a fifth layer 5a is formed with a surplus film thickness and a formed concave portion 7 affected by the fourth layer is polished by a CMP (Chemical Mechanical Polishing) method as shown in FIG. 1B or a method of smoothing by depositing a SOG film 8 as shown in FIG. 1C, has been thought.
In a liquid crystal display apparatus, there is also a problem that an uneven surface of interlayer dielectric from the wirings results in irregularly rubbing of an orientation film, disruption of alignment of liquid crystal is generated by the irregularly rubbing, which causes reduction of display quality. In the liquid crystal display apparatus, by using an organic dielectric film which is applied in a liquid state and heated, the organic dielectric film is deposited thick to form a flat surface.
In the semiconductor device in which the wirings are multilayered in order to increase the integration, parasitic capacitance is generated in a manner that wirings and gate electrodes formed in different layers are close to each other through the interlayer dielectric, which causes a problem that working speed is reduced. Accordingly, the interlayer dielectric tends to be formed thickly.
However, there &e a problem of dishing that polishing speed varies locally by density of pattern formed in a layer lower than a layer to be polished and a problem of contamination of the substrate caused by polishing wastage and waste (polishing) solution generated in a polishing treatment. There is a problem that a surface of the wirings is damaged by more polishing than necessity to reduce the reliability in the CMP method. There are a material being able to polish and a material being not able to polish in the CMP method, the CMP method can not be always applied to produce the all semiconductor devices.
Though it is thought that a dummy pattern is provided in order to eliminate a difference in density of pattern as a solution of the problem of dependence on the density of pattern described above, design flexibility is reduced by forming dummy pattern, and there is another problem that an open area ratio is reduced in the display apparatus.
It is possible that the polishing technique of the CMP method can apply to the semiconductor device formed on a silicon wafer and a quartz substrate which have flatness, however there is a problem that it is difficult that the CMP method applies to the semiconductor device formed on a large glass substrate and a flexible plastic substrate which have a large wave on their surface.
There are problems of planarization by using the SOG film described below. The SOG film is a film formed by heating treatment after a material for dielectric film dispersed in a solvent is coated on a surface of a wafer by a spin-coater. Though the SOG film is used as the planarization because the coated film is formed thinly in a concave portion and thickly in a convex portion by surface tension, the coated film causes corrosion of the metal wirings because of high hygroscopicity, which results the reliability to be reduced. For this reason additional process is required in order to form a film for protecting the metal wirings or a protective film for preventing moisture absorption, and as a result another problem of increment of process creates. In characteristics of the SOG film, there are problems such as high water penetration, easy deterioration, and easy cracking.
There is also a problem that many treatment steps are required for the smoothing treatment such that the SOG film is heated after the film material is coated to be equal to an oxide silicon film, furthermore the film in an unnecessary region is etched to remove and the protective layer is formed, and the film absorbs moisture during the process.
There is a problem that it is difficult to smooth an area where the number of elements per unit of area is large (for example, an area where circuits are close like a driving circuit and a functional circuit) and an area where the number of elements per unit of area is small (for example, an area like a pixel element where an open area is enlarged to extend an area in which light is transmitted) in the same state.
In the display apparatus, there is a problem that, when a kind of the film of the interlayer dielectric is different, index refraction is varied and the light is scattered to an unexpected direction at an interface to be incident on a semiconductor layer of the TFT, which causes light leak current.
In case that the wirings are multilayered to increase the integration, there are problems such that it takes long time to make a contact hole for conducting when the interlayer dielectric is formed thickly in order to reduce the parasitic capacitance generated between wirings in different layers, and since the formed contact hole has a large aspect ratio, a sufficient coverage is not achieved by sputtering deposition which is often used in case of forming wirings, which causes the wirings in a bottom surface of the contact hole not to be formed, accordingly reliability concerning the contact hole is reduced by disconnection of the wirings.
In view of the foregoing, it is an object of the invention to provide a method for smoothing easily without polishing treatment by the CMO method, smoothing treatment by the SOG film deposition and selecting substrate material in the semiconductor device formed by a multilayer including a plurality of layers with various materials and formed patterns. It is another object of the invention to provide a method of smoothing which is so contrived that thickening interlayer dielectric required for reducing parasitic capacitance generated between wirings of different layers is compatible with thinning interlayer dielectric required for increasing reliability concerning the contact hole.